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LTC3707EGN-SYNC Datasheet(PDF) 9 Page - Linear Technology |
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LTC3707EGN-SYNC Datasheet(HTML) 9 Page - Linear Technology |
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9 / 32 page  LTC3707-SYNC 9 3707sfa FUCTIONAL DIAGRAM SWITCH LOGIC – + 0.8V 4.8V 5V VIN VIN 4.5V BINH CLK2 CLK1 0.18μA R6 R5 + – FCB + – – + – + – + VREF INTERNAL SUPPLY 3.3VOUT VSEC RLP CLP 3V FCB EXTVCC INTVCC SGND + 5V LDO REG SW SHDN 0.55V TOP BOOST TG CB CIN D1 DB PGND BOT BG INTVCC INTVCC VIN + CSEC COUT VOUT 3707 FD/F02 DSEC RSENSE R2 VOSENSE DROP OUT DET RUN SOFT START BOT TOP ON S R Q Q OSCILLATOR PHASE DET PLLFLTR PLLIN FCB EA 0.86V 0.80V OV VFB 1.2μA 6V R1 – + RC 4(VFB) RST SHDN RUN/SS ITH CC CC2 CSS 4(VFB) 0.86V SLOPE COMP 3mV + – – + SENSE– SENSE+ INTVCC 30k 45k 2.4V 45k 30k I1 I2 B DUPLICATE FOR SECOND CONTROLLER CHANNEL + – – + 50k FIN + – + – + – + – PGOOD VOSENSE1 VOSENSE2 0.86V 0.74V 0.86V 0.74V OPERATION (Refer to Functional Diagram) Main Control Loop The IC uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSEpinreceivesthevoltagefeedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET Figure 2 |
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