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LTC4263IDE-TRPBF Datasheet(PDF) 3 Page - Linear Technology |
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LTC4263IDE-TRPBF Datasheet(HTML) 3 Page - Linear Technology |
3 / 16 page LTC3544B 3 3544bfa Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3544BE is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD)(68°C/W). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRUN(HIGH) RUNx Input High Voltage ● 1.0 V VRUN(LOW) RUNx Input Low Voltage ● 0.3 V ILSW SWx Leakage VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V ±0.1 ±1 μA IRUN RUN Leakage Current VIN = 5.5V ● ±0.1 ±1 μA IVFB VFBx Leakage Current 80 nA tSS Soft-Start Period VFB = 7.5% to 92.5% Full Scale 650 875 1200 μs VUVLO Undervoltage Lockout ● 1.9 2.25 V Individual Regulator Characteristics Regulator SW300 – 300mA IPK Peak Switch Current Limit VFB < VFBREG, Duty Cycle < 35% 400 600 800 mA IS300 Input DC Bias Current–Reg SW300 Only Active Mode (Pulse Skip) VFB = 0.7V, ILOAD = 0A, 2.25MHz 320 μA RPFET RDS(ON) of P-Channel FET (Note 7) ISW = 100mA 0.55 Ω RNFET RDS(ON) of N-Channel FET (Note 7) ISW = –100mA 0.50 Ω Regulator SW200A – 200mA IPK Peak Switch Current Limit VFB < VFBREG, Duty Cycle < 35% 300 400 500 mA IS200 Input DC Bias Current–Reg SW200A Only Active Mode (Pulse Skip) VFB = 0.7V, ILOAD = 0A, 2.25MHz 320 μA RPFET RDS(ON) of P-Channel FET (Note 7) ISW = 100mA 0.65 Ω RNFET RDS(ON) of N-Channel FET (Note 7) ISW = –100mA 0.60 Ω Regulator SW200B – 200mA IPK Peak Switch Current Limit VFB < VFBREG, Duty Cycle < 35% 300 400 500 mA IS200 Input DC Bias Current–Reg SW200B Only Active Mode (Pulse Skip) VFB = 0.7V, ILOAD = 0A, 2.25MHz 320 μA RPFET RDS(ON) of P-Channel FET (Note 7) ISW = 100mA 0.65 Ω RNFET RDS(ON) of N-Channel FET (Note 7) ISW = –100mA 0.60 Ω Regulator SW100 – 100mA IPK Peak Switch Current Limit VFB < VFBREG, Duty Cycle < 35% 200 300 400 mA IS100 Input DC Bias Current–Reg SW100B Only Active Mode (Pulse Skip) VFB = 0.7V, ILOAD = 0A, 2.25MHz 320 μA RPFET RDS(ON) of P-Channel FET (Note 7) ISW = 100mA 0.80 Ω RNFET RDS(ON) of N-Channel FET (Note 7) ISW = –100mA 0.75 Ω ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC3544B is tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 6: Load regulation is inferred by measuring the regulation loop gain. Note 7: The QFN switch on-resistance is guaranteed by correlation to wafer level measurements. Note 8: Guaranteed by long-term current density limitations. |
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