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LTC3407AIDD-2-TRPBF Datasheet(PDF) 10 Page - Linear Technology |
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LTC3407AIDD-2-TRPBF Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LTC3407A-2 10 3407a2f Power-On Reset The POR pin is an open-drain output which pulls low when either regulator is out of regulation. When both output voltages are within ±8.5% of regulation, a timer is started which releases POR after 216 clock cycles (about 29ms in pulse skipping mode). This delay can be significantly longer in Burst Mode operation with low load currents, since the clock cycles only occur during a burst and there could be milliseconds of time between bursts. This can be bypassed by tying the POR output to the MODE/SYNC input, to force pulse skipping mode during a reset. In addition, if the output voltage faults during Burst Mode sleep, POR could have a slight delay for an undervoltage output condition and may not respond to an overvoltage output. This can be avoided by using pulse skipping mode instead. When either channel is shut down, the POR output is pulled low, since one or both of the channels are not in regulation. Mode Selection & Frequency Synchronization The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. Connect- ing this pin to VIN enables Burst Mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected to ground, pulse skipping operation is selected which pro- vides the lowest output ripple, at the cost of low current efficiency. The LTC3407A-2 can also be synchronized to another LTC3407A-2 by the MODE/SYNC pin. During synchroni- zation, the mode is set to pulse skipping and the top switch turn-on is synchronized to the rising edge of the external clock. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by theregulatortoreturnVOUTtoitssteady-statevalue.During APPLICATIO S I FOR ATIO At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approxi- mately: C I fV OUT OUT O DROOP ≈ Δ 3 • More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely re- quired to supply high frequency bypassing, since the impedance to the supply is very low. A 10 μF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3407A-2 develops a 0.6V reference voltage be- tween the feedback pin, VFB, and ground as shown in Figure 1. The output voltage is set by a resistive divider according to the following formula: VV R R OUT =+ ⎛ ⎝⎜ ⎞ ⎠⎟ 06 1 2 1 . Keeping the current small (<5 μA) in these resistors maxi- mizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward ca- pacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. |
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