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LTC3407EDD-4 Datasheet(PDF) 11 Page - Linear Technology |
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LTC3407EDD-4 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 16 page  LTC3407-4 11 34074f produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in LTC3407-4 circuits: 1)VIN quiescent current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the Electrical Characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continu- ous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other ‘hidden’ losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching fre- quency. Other losses including diode conduction losses during dead-time and inductor core losses generally ac- count for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3407-4 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3407-4 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150 °C, both power switches will turn off and the SW node will become high impedance. To prevent the LTC3407-4 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The tempera- ture rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3407-4 is in dropout on both channels at an input voltage of 2.7V with a load current of 800mA and an ambient temperature of 70 °C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the main switch is 0.425 Ω. Therefore, power dissipated by each channel is: PD = I2 • RDS(ON) = 272mW The MS package junction-to-ambient thermal resistance, θJA, is 45°C/W. Therefore, the junction temperature of the APPLICATIO S I FOR ATIO |
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