 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AIC1384 Datasheet(PDF) 10 Page - Analog Intergrations Corporation |
|
||||||||||||||||||||||||||||||
AIC1384 Datasheet(HTML) 10 Page - Analog Intergrations Corporation |
|
|
10 / 15 page  AIC1384 10 APPLICATION INFORMATION The AIC1384 linear termination regulator is designed to meet JEDEC requirements of DDR- SDRAM (DDRⅠ/Ⅱ). The VTT is able to deliver sinking and sourcing current while regulating the voltage equal to VDDQ/2. The output stage includes a sense function to maintain excellent load regulation to prevent shoot through. The power part has two distinct rails that split the internal analog circuitry from power output stage, which results in reducing internal power disspation. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is necessary to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The achievement of single parallel termination can be seen as below figure. RT RS Memory VTT VIN ChipSet VREF Between the chipset and memory are one RS series resistor and one RT termination resistor. Both RS and RT are 25 Ohms typically; they can be altered to scale the current requirements from the AIC1384. AVIN and PVIN AVIN and PVIN have the ability to work with separate supplies depending on the application. Higher PVIN will increase the maximum continuous output current resulting from output RDS-ON limitations at voltages close to VTT. Oppositely, the internal power dissipation will also increase at high PVIN. Connect AVIN and PVIN together with 2.5V is a good compromise in SSTL-2 applications. This reduces the need for bypassing two supply pins separately. For the safe operation of the system; AVIN must always exceed or equal to PVIN. VDDQ VDDQ is used to make internal reference voltage for regulating VTT. And VTT will track VDDQ/2 precisely because of internal resistor divider. For SSTL-2 application, connect VDDQ to the 2.5V rail directly at the DIMM instead of AVIN and PVIN to achieve that reference voltage tracks the DDR memory rails accurately without a voltage drop from power lines. VSENSE The sense pin is used to improve remote load regulation. The termination resistors in most motherboards connect to VTT with a long trace that will cause a significant voltage drop. The VSENSE pin can improve that a lower termination voltage at one end of the bus than the other by connecting it to the middle of the bus. If a long VSENSE trace is implemented close to the memory, noise pickup can be a problem in precise regulation of VTT. A small 0.1µF ceramic capacitor can be used for filtering noise. VSENSE pin must still tie to VTT if remote load regulation is not used. VREF VREF provides the buffered output of the internal VDDQ/2 reference voltage. It can be used to support the reference voltage for the Northbridge chipset and memory. The VREF remains active during the shutdown state and thermal shutdown for the Suspend to RAM functionality. A bypass capacitor, located close to the VREF pin, can be used to improve performance. Ranging from |
Similar Part No. - AIC1384 |
|
Similar Description - AIC1384 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
