LTC2934CDC-2-TRPBF datasheet(7/12 Pages) LINER

Part #	LTC2934CDC-2-TRPBF

Description	Ultra-Low Power Adjustable Supervisor with Power-Fail Output

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Manufacturer	LINER [Linear Technology]

Direct Link	http://www.linear.com

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LTC2934

7

2934f

APPLICATIONS INFORMATION

VOLTAGE MONITORING

Unmanaged power can cause various system problems.

At power-up, voltage ﬂuctuation around critical thresholds

can cause improper system or processor initialization.

The LTC2934 provides power management capabilities

for the system power-up phase. The supervisory device

issues a system reset after the monitored voltage has

stabilized. Built-in hysteresis and ﬁltering ensures that

ﬂuctuations due to load transients or supply noise do

not cause chattering of the status outputs. Comparator

undervoltage glitch immunity is shown in the Typical

Performance Characteristics section. The curve dem-

onstrates the transient amplitude and width required to

switch the comparators.

Because many batteries exhibit large series resistance,

load currents can cause signiﬁcant voltage drops. The

low DC current draw of the LTC2934 (at any input volt-

age) does not add to the loading problem. When voltage

is initially applied to VCC, RST and PFO pull low once there

is enough voltage to turn on the pull-down devices (1V

maximum).

If the monitored supply voltage falls to the power-fail

threshold, the built-in power-fail comparator pulls PFO low.

PFO remains low until the PFI input rises above 0.4V plus

2.5% hysteresis. PFO is typically used to signal preparation

for controlled shutdown. For example, the PFO output may

be connected to a processor nonmaskable interrupt. Upon

interrupt, the processor begins shutdown procedures such

as supply sequencing and/or storage/erasure of system

state in nonvolatile memory.

If the monitored voltage drops below the reset threshold,

RST pulls low until the ADJ input rises above 0.4V plus

5% hysteresis. This may occur through battery charging

or replacement. An internal reset timer delays the return

of the RST output to a high state to provide settling and

initialization time. The RST output is typically connected

to processor reset input.

Few, if any external components are necessary for reliable

operation. However, a decoupling capacitor between VCC

and ground is recommended (0.01μF minimum).

Threshold Conﬁguration

The LTC2934 monitors voltage applied to its inputs PFI and

ADJ. A resistive divider connected between a monitored

voltage and ground is used to bias the inputs. Figure 1

demonstrates how the monitor inputs can be made de-

pendent upon a single voltage (V1). Only three resistors

are required. To calculate their values, specify desired

falling power fail (VPF) and reset voltages (VR) with VPF

> VR. For example:

VPF = 1.72V, VR = 1.62V

Figure 1. Conﬁguration for Single Voltage Monitoring

2934 F01

ADJ

R3

PFI

LTC2934

V1

R2

R1

The solution for R1, R2, and R3 provides three equations

and three unknowns. Maximum resistor size is governed

by maximum input leakage current. For the LTC2934, the

maximum input leakage current over temperature is 1nA.

For a maximum error of 1% due to both input currents,

the resistor divider current should be 100 times the sum

of the leakage currents, or 0.2μA. At the reset threshold,

V1 = 1.62V, so RSUM = V1/0.2μA = 8.1M where:

RSUM = R1 + R2 + R3

The falling monitor thresholds (VTH) are 0.4 volts, so:

R

VR

V

VM

V

M

TH

SUM

PF

1

04

81

172

188

==

=

•.

• .

.

The closest 1% value is 1.87M. R2 can be determined

from:

R

VR

V

R

VM

V

M

R

TH

SUM

R

21

04

81

162

187

2

130

==

−

=

•

–

.• .

.

kk

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LTC2934CDC-2-TRPBF Datasheet(PDF) 7 Page - Linear Technology

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