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LTC2751AIUHF-16-TRPBF Datasheet(PDF) 5 Page - Linear Technology

Part # LTC2751AIUHF-16-TRPBF
Description  Current Output 12-/14-/16-Bit SoftSpanTM DACs with Parallel I/O
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2751AIUHF-16-TRPBF Datasheet(HTML) 5 Page - Linear Technology

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LTC2751
5
2751f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7V to 3.3V
Write and Update Timing
t1
I/O Valid to ⎯W⎯R Rising Edge Set-Up
18
ns
t2
I/O Valid to ⎯W⎯R Rising Edge Hold
18
ns
t3
⎯W⎯R Pulse Width
30
ns
t4
UPD Pulse Width
30
ns
t5
UPD Falling Edge to ⎯W⎯R Falling Edge
No Data Shoot-Through
0ns
t6
⎯W⎯R Rising Edge to UPD Rising Edge
(Note 10)
0ns
t7
⎯D/S Valid to ⎯W⎯R Falling Edge Set-Up Time
18
ns
t8
⎯W⎯R Rising Edge to ⎯D/S Valid Hold Time
18
ns
Readback Timing
t13
⎯W⎯R Rising Edge to Read Rising Edge
18
ns
t14
Read Falling Edge to ⎯W⎯R Falling Edge
(Note 10)
40
ns
t15
Read Rising Edge to I/O Propagation Delay
CL = 10pF
40
ns
t17
UPD Valid to I/O Propagation Delay
CL = 10pF
40
ns
t18
⎯D/S Valid to Read Rising Edge
(Note 10)
18
ns
t19
Read Rising Edge to UPD Rising Edge
No Update
9ns
t20
UPD Falling Edge to Read Falling Edge
No Update
9ns
t22
READ Falling Edge to UPD Rising Edge
(Note 10)
18
ns
t23
I/O Bus Hi-Z to Read Rising Edge
(Note 10)
0ns
t24
Read Falling Edge to I/O Bus Active
(Note 10)
40
ns
⎯C⎯L⎯R Timing
t25
⎯C⎯L⎯R Pulse Width Low
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to
RCOM.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
TIMING CHARACTERISTICS V
DD = 5V, VREF = 5V unless otherwise specified. The denotes specifications that
apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
basis. See Application Note 74, “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.”
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 9. Calculation from Vn = √⎯4⎯k⎯T⎯R⎯⎯⎯B, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 10. Guaranteed by design. Not production tested.


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