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LTC2484 Datasheet(PDF) 5 Page - Linear Technology |
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LTC2484 Datasheet(HTML) 5 Page - Linear Technology |
5 / 40 page 5 LTC2484 2484fa SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fEOSC External Oscillator Frequency Range (Note 15) ● 10 4000 kHz tHEO External Oscillator High Period ● 0.125 100 µs tLEO External Oscillator Low Period ● 0.125 100 µs tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode ● 157.2 160.3 163.5 ms 60Hz Mode ● 131.0 133.6 136.3 ms Simultaneous 50Hz/60Hz Mode ● 144.1 146.9 149.9 ms External Oscillator ● 41036/fEOSC (in kHz) ms tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode ● 78.7 80.3 81.9 ms 60Hz Mode ● 65.6 66.9 68.2 ms Simultaneous 50Hz/60Hz Mode ● 72.2 73.6 75.1 ms External Oscillator ● 20556/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 38.4 kHz External Oscillator (Notes 10, 11) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) ● 45 55 % fESCK External SCK Frequency Range (Note 10) ● 4000 kHz tLESCK External SCK Low Period (Note 10) ● 125 ns tHESCK External SCK High Period (Note 10) ● 125 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 0.81 0.83 0.85 ms External Oscillator (Notes 10, 11) ● 256/fEOSC (in kHz) ms tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 10) ● 32/fESCK (in kHz) ms t1 CS ↓ to SDO Low ● 0 200 ns t2 CS ↑ to SDO High Z ● 0 200 ns t3 CS ↓ to SCK↓ (Note 10) ● 0 200 ns t4 CS ↓ to SCK↑ (Note 10) ● 50 ns tKQMAX SCK ↓ to SDO Valid ● 200 ns tKQMIN SDO Hold After SCK ↓ (Note 5) ● 15 ns t5 SCK Set-Up Before CS ↓ ● 50 ns t6 SCK Hold After CS ↓ ● 50 ns t7 SDI Setup Before SCK ↑ (Note 5) ● 100 ns t8 SDI Hold After SCK ↑ (Note 5) ● 100 ns The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) TI I G CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2 Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as digital input and the driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: Refer to Applications Information section for performance vs data rate graphs. |
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