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LTC2360IS6-TRMPBF Datasheet(PDF) 15 Page - Linear Technology |
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LTC2360IS6-TRMPBF Datasheet(HTML) 15 Page - Linear Technology |
15 / 20 page LTC2360/LTC2361/LTC2362 15 236012f APPLICATIONS INFORMATION ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 0.5mA, 0.75mA and 1.1mA for the LTC2360/LTC2361/LTC2362 and automati- cally entering sleep mode right after a conversion, these devices achieve extremely low power consumption over a wide range of sample rates (see Figure 11). The sleep mode allows the supply current to drop with reduced sample rate. Several things must be taken into account to achieve such low power consumption. Minimize Power Consumption in Sleep Mode The LTC2360/LTC2361/LTC2362 enter sleep mode after each conversion if CONV remains high and draw only leakage current (see Figure 10). If the CONV input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CONV pin to GND when it is low and to VDD when it is high. After the conversion with CONV staying high, the converter is in sleep mode and draws only leakage current. The status of the SCK input has no effect on supply current during this time. For the best performance, hold SCK either high or low while the ADC is converting. Minimize the Device Active Time In systems that have significant time between conversions, the ADC draws a minimal amount of power. Figures 12 and 13 show two ways to minimize the amount of time the ADC draws power. In Figure 12, the ADC draws power during tACQ and tCONV and is in sleep mode for the rest of the time. The conversion results are available at the next CONV falling edge. In Figure 13, the ADC draws twice the power than that in Figure 12, but the conversion results are available during tDATA. The user can use the fastest SCK available in the system to shorten data transfer time, tDATA as long as t4 and t7 are not violated. SDO Loading Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the SDO pin can add more than 50μA to the supply current at a 200kHz clock frequency. An extra 50μA or so of current goes into charg- ing and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C • V • f currents must be evaluated with the troublesome ones minimized. Figure 11. Supply Current vs Sample Rate RECOMMENDED HIGH OR LOW Hi-Z STATE 236012 F12 B11 CONV SCK SDO 12 3 4 9 10 11 12 B10 B9 B3 B2 B1 B0 SAMPLING INPUT AND TRANSFERRING DATA EXECUTING A CONVERSION AND PUTTING THE DEVICE INTO SLEEP MODE tACQ tCONV SLEEP MODE tTHROUGHPUT = tACQ + tCONV + tSLEEPMODE Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up SAMPLE RATE (ksps) 236012 TA01b 1200 1000 800 400 600 200 0 1 100 1000 10 VDD = OVDD = VREF = 3.6V TA = 25°C LTC2361 LTC2362 LTC2360 |
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