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LTC2272CUJ Datasheet(PDF) 1 Page - Linear Technology |
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LTC2272CUJ Datasheet(HTML) 1 Page - Linear Technology |
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1 / 44 page  LTC2273/LTC2272 1 22732f TYPICAL APPLICATION FEATURES APPLICATIONS DESCRIPTION 16-Bit, 80Msps/65Msps Serial Output ADC The LTC®2273/LTC2272 are 80Msps/65Msps, 16-bit A/D converters with a high speed serial interface. They are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC serial interface for data converters specification (JESD204). The LTC2273/LTC2272 are perfect for demanding applica- tions where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature. The encode clock inputs, ENC+ and ENC–, may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n High Speed Serial Interface (JESD204) n Sample Rate: 80Msps/65Msps n 77.7dBFS Noise Floor n 100dB SFDR n SFDR >90dB at 140MHz (1.5VP-P Input Range) n PGA Front End (2.25VP-P or 1.5VP-P Input Range) n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Single 3.3V Supply n Power Dissipation: 1100mW/990mW n Clock Duty Cycle Stabilizer n Pin Compatible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272 n 40-Pin 6mm × 6mm QFN Package n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE – + S/H AMP CORRECTION LOGIC 8B/10B ENCODER 16-BIT PIPELINED ADC CORE INTERNAL ADC REFERENCE GENERATOR 1.25V COMMON MODE BIAS VOLTAGE CLOCK/DUTY CYCLE CONTROL SCRAMBLER/ PATTERN GENERATOR PLL 20X ENC+ ENC– VCM ANALOG INPUT 22732 TA01 SYNC+ SYNC – OVDD 3.3V 1.2V TO 3.3V 3.3V FAM ASIC OR FPGA SENSE CLOCK 2.2μF PAT1 PAT0 SRR1 SRR0 SCRAM SHDN MSBINV DITH PGA 0.1μF 0.1μF 0.1μF VDD GND AIN + AIN – CMLOUT+ CMLOUT– 16 20 – + SERIALIZER SERIAL RECEIVER 50Ω 50Ω 128k Point FFT, fIN = 4.93MHz, –1dBFS, PGA = 0 FREQUENCY (MHz) 0 10 20 30 40 22732 G04 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 |
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