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LTC2242-12 Datasheet(PDF) 10 Page - Linear Technology |
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LTC2242-12 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LTC2242-12 10 224212f PI FU CTIO S (LVDS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN– (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1 µF ceramic chip capacitor, to Pins 11, 12 with a 2.2 µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1 µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1 µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1 µF ceramic chip capacitor, to Pins 5, 6 with a 2.2 µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1 µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1 µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connect- ing SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100 Ω termination resistors at the LVDS re- ceiver. D11–/D11+ is the MSB. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1 µF ceramic chip capacitor. CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simulta- neous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2 µF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. |
Similar Part No. - LTC2242-12 |
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Similar Description - LTC2242-12 |
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