Electronic Components Datasheet Search |
|
LTM2220IV-AA-PBF Datasheet(PDF) 9 Page - Linear Technology |
|
LTM2220IV-AA-PBF Datasheet(HTML) 9 Page - Linear Technology |
9 / 12 page LTM2220-AA 9 2220aaf APPLICATIONS INFORMATION Any noise present on the encode signal will result in ad- ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the ampli- tude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The clock inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates ThemaximumencoderatefortheLTM2220-AAis170Msps. For the ADC to operate properly, the encode signal should have a 50% (±20%) duty cycle. Each half cycle must have at least 2ns for the ADC internal circuitry to have enough settling time for proper operation. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. The lower limit of the LTM2220-AA sample rate is de- termined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM2220-AA is 1Msps. VDD VDD LTM2220-AA 2220 F03 VDD CLK– CLK+ 1.6V BIAS 1.6V BIAS 1:4 0.1 µF CLOCK INPUT 50 Ω 6k 6k TO INTERNAL ADC CIRCUITS Figure 3. Transformer Driven CLK+/CLK– 2220 F04 CLK– 1.6V VTHRESHOLD = 1.6V CLK+ 0.1 µF LTM2220-AA 2220 F05 CLK– CLK+ 130 Ω 3.3V 3.3V 130 Ω D0 Q0 Q0 MC100LVELT22 LTM2220-AA 83 Ω 83 Ω Figure 5. CLK Drive Using a CMOS to PECL Translator Figure 4. Single-Ended CLK Drive, Not Recommended for Low Jitter |
Similar Part No. - LTM2220IV-AA-PBF |
|
Similar Description - LTM2220IV-AA-PBF |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |