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LTC1864L Datasheet(PDF) 9 Page - Linear Technology

Part No. LTC1864L
Description  μPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC1864L Datasheet(HTML) 9 Page - Linear Technology

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9
LTC1864L/LTC1865L
sn18645L 18645Lfs
LTC1864L OPERATION
Operating Sequence
The LTC1864L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1864L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1864L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Analog Inputs
The LTC1864L has a unipolar differential analog input. The
converter will measure the voltage between the “IN+” and
“IN” inputs. A zero code will occur when IN+ minus IN
equals zero. Full scale occurs when IN+ minus INequals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and VREF is tied to VCC, a rail-to-rail input span
will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864L
defines the full-scale range of the A/D converter. The
LTC1864L can operate with reference voltages from VCC to
1V.
CONV
tCONV
SCK
SDO
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B15 B14
B12
B10
B8
B6
B4
B2
B0*
Hi-Z
1854 F01
Hi-Z
B13
B11
B9
B7
B5
B3
B1
SLEEP MODE
tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
DON'T CARE
1
2
3
4
8
7
6
5
VREF
IN+
IN
GND
VCC
SCK
SDO
CONV
LTC1864L
1864 F03
VIN = 0V TO VCC
VCC
1µF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Figure 1. LTC1864L Operating Sequence
Figure 3. LTC1864L with Rail-to-Rail Input Span
Figure 2. LTC1864L Transfer Curve
VIN*
*VIN = IN
+ – IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1864 F02
APPLICATIO S I FOR ATIO


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