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LTC1852 Datasheet(PDF) 15 Page - Linear Technology |
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LTC1852 Datasheet(HTML) 15 Page - Linear Technology |
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15 / 24 page  LTC1852/LTC1853 15 18523fa BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1852/LTC1853, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog inputs, reference or analog power supply lines. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 34 (OGND), Pin 13 (GND), Pin 16 (GND) and all other analog grounds should be connected to this single ana- log ground point. The bypass capacitors should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. In some applications, it may be desirable to connect the OVDD to the logic system supply and OGND to the logic system ground. In these cases, OVDD should be bypassed to OGND instead of the analog ground plane. Low impedance analog and digital power supply common returns are essential to the low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously ac- tive microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the sucessive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversions or by using three-state buffers to isolate the ADC bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1852/LTC1853 have differential inputs to mini- mize noise coupling. Common mode noise on the “+” and “–” inputs will be rejected by the input CMRR. The LTC1852/LTC1853 will hold and convert the difference between whichever input is selected as the “+” input and whichever input is selected as the “–” input. Leads to the inputs should be kept as short as possible. SUPPLY BYPASSING High quality, low series resistance ceramic 10μF bypass capacitors should be used. Surface mount ceramic ca- pacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10μF tantalum capacitors in parallel with 0.1μF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. DIGITAL INTERFACE Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 1400ns, and a maximum conversion time over the full operating temperature range of 2μs. No external adjustments are required. The guaranteed maximum acquisition time is 150ns. In addition, a throughput time of 2.5μs and a minimum sampling rate of 400ksps is guaranteed. SHDN CONVST t4 18523 F03 CS SHDN t3 18523 F02 Figure 3. SHDN to CONVST Wake-Up Timing Figure 2. CS to SHDN Setup Timing APPLICATIONS INFORMATION |
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Similar Description - LTC1852 |
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