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LTC1773EMS-TRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC1773EMS-TRPBF Datasheet(HTML) 11 Page - Linear Technology |
11 / 20 page LTC1773 11 1773fb Synchronous switching removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With continuous synchronous operation, power can be drawn from the auxiliary windings without regard to the primary output load. The secondary output voltage is set by the turns ratio of the transformer in conjunction with a pair of external resistors returned to the SYNC/FCB pin as shown in Figure 5. The secondary regulated voltage, VSEC, in Figure 5 is given by: VN V V V R R SEC OUT DIODE ≅ + () − >+ ⎛ ⎝⎜ ⎞ ⎠⎟ 10 8 1 4 3 . where N is the turns ratio of the transformer and VOUT is the main output voltage sensed by VFB. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1773 circuits: VIN quiescent current, external power MOSFET gate charge current, I2R losses, and topside MOSFET transition losses. 1. The VIN quiescent current is due to the DC bias current as given in the electrical characteristics, it excludes MOSFET driver and control currents. VIN current results in a small loss which increases with VIN. 2. The external MOSFET gate charge current results from switching the gate capacitance of the external power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN; it is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the external main and synchronous switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply volt- ages. 3. I2R losses are calculated from the resistances of the external RSENSE, the external power MOSFETs (RSW) and the external inductor (RL). In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchro- nous switch. Thus, the series resistance looking into the SW pin from L is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC), as follows: RSW = (RDS(ON)TOP +RSENSE) • DC + RDS(ON)BOT • (1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the MOSFET manufactures’s datasheets. Thus, to obtain I2R losses, simply add RSW and RL together and multiply their sum by the square of the average output current. 4. Transition losses apply to the topside MOSFET and increase when operating at high input voltages and higher operating frequencies. Transition losses can be estimated from: Transition Loss = 2(VIN)2IO(MAX)CRSS(f) APPLICATIONS INFORMATION Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Figure 5. Secondary Output Loop Connection LTC1773 + + R4 R3 1 µF VOUT VSEC COUT L1 1:N SYNC/FCB BG SW TG 1773 F05 VIN |
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