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LTC1745CFW Datasheet(PDF) 11 Page - Linear Technology |
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LTC1745CFW Datasheet(HTML) 11 Page - Linear Technology |
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11 / 20 page  11 LTC1745 1745f CONVERTER OPERATION As shown in Figure 1, the LTC1745 is a CMOS pipelined multistep converter. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. The en- code input is also differential for improved common mode noise immunity. The LTC1745 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. APPLICATIO S I FOR ATIO DIFF REF AMP REF BUF INTERNAL CLOCK SIGNALS INTERNAL REFERENCES TO ADC DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER RANGE SELECT 2.35V REFERENCE ENC ENC OUTPUT DRIVERS SHIFT REGISTER AND CORRECTION OE MSBINV OGND OF OVDD 0.5V TO 5V D11 D0 CLKOUT 1745 F01 INPUT S/H FIRST STAGE SENSE VCM AIN – AIN + 4.7 µF SECOND STAGE THIRD STAGE FOURTH STAGE • • • 5-BIT PIPELINED ADC STAGE 4-BIT PIPELINED ADC STAGE 4-BIT PIPELINED ADC STAGE 4-BIT FLASH ADC CONTROL LOGIC REFLA REFHB 4.7 µF 1 µF1µF 0.1 µF 0.1 µF REFHA REFLB Figure 1. Functional Block Diagram |
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