6

LTC4440

4440f

TI I G DIAGRA

90%

10%

INPUT (INP)

OUTPUT (TG)

INPUT RISE/FALL TIME < 10ns

4440 TD

BLOCK DIAGRA

BOOST

TS

GND

TG

BOOST

4440 BD

UP TO 80V,

TRANSIENT

UP TO 100V

TS

HIGH SIDE

UNDERVOLTAGE

LOCKOUT

UNDERVOLTAGE

LOCKOUT

LEVEL SHIFTER

8V TO 15V

GND

INP

Exposed Pad MS8E Package

INP (Pin 1): Input Signal. TTL/CMOS compatible input

referenced to GND (Pin 2).

GND (Pins 2, 4): Chip Ground.

side circuitry. A low ESR ceramic bypass capacitor should

be tied between this pin and the GND pin (Pin 2).

NC (Pin 5): No Connect. No connection required. For

convenience, this pin may be tied to Pin 6 (BOOST) on the

application board.

BOOST (Pin 6): High Side Bootstrapped Supply. An exter-

nal capacitor should be tied between this pin and TS

(Pin 8). Normally, a bootstrap diode is connected between

drop of the bootstrap diode.

TG (Pin 7): High Current Gate Driver Output (Top Gate).

This pin swings between TS and BOOST.

TS (Pin 8): Top (High Side) Source Connection.

Exposed Pad (Pin 9): Ground. Must be electrically con-

nected to Pins 2 and 4 and soldered to PCB ground for

optimum thermal performance.

PI FU CTIO S