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LTC4403-1 Datasheet(PDF) 4 Page - Linear Technology |
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LTC4403-1 Datasheet(HTML) 4 Page - Linear Technology |
4 / 12 page 4 LTC4403-1/LTC4403-2 4403f GND (Pin 4/5): System Ground. PCTL (Pin 5/6): Analog Input. The external power control DAC drives this input. The amplifier servos the RF power until the RF detected signal equals the DAC signal applied at this pin. SHDN (Pin 6/7): Shutdown Input. A logic low on the SHDN pin places the part in shutdown mode. A logic high enables the part after 10 µs. SHDN has an internal 150k pull-down resistor to ensure that the part is in shutdown when no input is applied. In shutdown, VPCAand VPCBare pulled to ground via a 112 Ω resistor. (LTC4403-1/LTC4403-2) PI FU CTIO S VHOLD (Pin 7/8): Asserted high prior to AM modulation, opens control loop and holds voltage at VPCAorVPCBduring EDGE modulation. BSEL (Pin 9): (LTC4403-2 Only) Selects VPCA when low and VPCB when high. This input has an internal 150k resistor to ground. RF (Pin 8/10): Coupled RF Feedback Voltage . This input is referenced to VIN. The frequency range is 300MHz to 2400MHz. This pin has an internal 250 Ω termination, an internal Schottky diode detector and peak detector capacitor. BLOCK DIAGRA (LTC4403-2) – + RFDET – + GM 70mV 270kHz FILTER – + 30k 22k 51k 30k 250 Ω 28pF 0.4pF ±0.05pF 12 Ω 100 Ω 100 Ω 4403 BD 12 Ω 150k 150k 150k BSEL PB PA 60 µA60µA RF 10 VIN Li-Ion 1 VPCA VPCB GND 9 PCTL 6 RF PA 850MHz/900MHz AZ AUTOZERO TXENB TXENB VHOLD + – + – MUX CONTROL VHOLD 8 7 SHDN RF PA DIPLEXER 1.8GHz/1.9GHz 5 50 Ω 9 µs DELAY GAIN COMPRESSION 2 3 CHOLD VIN VREF CREF BUFFER VHOLD VHOLD 38k + – 4 |
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Similar Description - LTC4403-1 |
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