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LTC1741 Datasheet(PDF) 16 Page - Linear Technology |
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LTC1741 Datasheet(HTML) 16 Page - Linear Technology |
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16 / 20 page  16 LTC1741 1741f down to low voltages. The internal resistor in series with the output makes the output appear as 50 Ω to external circuitry and may eliminate the need for external damping resistors. Output Loading As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1741 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43 Ω on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Format The LTC1741 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. When OF outputs a logic high the converter is either overranged or underranged. Output Clock The ADC has a delayed version of the ENC input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLKOUT falls and can be latched on the rising edge of CLKOUT. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For APPLICATIO S I FOR ATIO example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE low disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The voltage on OE can swing between GND and 0VDD. OE should not be driven above 0VDD. GROUNDING AND BYPASSING The LTC1741 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an inter- nal ground plane is recommended. The pinout of the LTC1741 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capaci- tors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7 µFcapacitorbetweenREFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1741 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. |
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Similar Description - LTC1741 |
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