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LTC1400CS8 Datasheet(PDF) 6 Page - Linear Technology |
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LTC1400CS8 Datasheet(HTML) 6 Page - Linear Technology |
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6 / 20 page  LTC1400 6 1400fa FU CTIO AL BLOCK DIAGRA 1400 BD01 12-BIT CAPACITIVE DAC COMP SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO SERIAL CONVERTER ZEROING SWITCH CONTROL LOGIC 2.42V REF DOUT VCC CONV CLK VREF AIN CSAMPLE 12 GND VSS 1400 TC01 DOUT DOUT 3k 3k CLOAD CLOAD Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 5V TEST CIRCUITS PI FU CTIO S VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10μF tantalum in parallel with 0.1μF ceramic). AIN(Pin2):AnalogInput.0Vto4.096V(Unipolar),±2.048V (Bipolar). VREF (Pin 3): 2.42V Reference Output. Bypass to GND (10μF tantalum in parallel with 0.1μF ceramic). GND (Pin 4): Ground. GND should be tied directly to an analog ground plane. DOUT (Pin 5): The A/D conversion result is shifted out from this pin. CLK (Pin 6): Clock. This clock synchronizes the serial data transfer. A minimum CLK pulse of 50ns will cause the ADC to wake up from Nap or Sleep mode. CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK low and pulsing CONV two/four times will put the ADC into Nap/Sleep mode. VSS (Pin 8): Negative Supply. –5V for bipolar operation. Bypass to GND with 0.1μF ceramic. VSS should be tied to GND for unipolar operation. |
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