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TS80C52X2-LCBB Datasheet(PDF) 24 Page - TEMIC Semiconductors |
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TS80C52X2-LCBB Datasheet(HTML) 24 Page - TEMIC Semiconductors |
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24 / 54 page  24 Rev. B - Jan. 25, 1999 Preliminary TS80C52X2 6.5 Interrupt System The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9. Figure 9. Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 11.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 12.) and in the Interrupt Priority High register (See Table 13.). shows the bit values and priority levels associated with each combination. IE1 0 3 High priority interrupt Interrupt polling sequence, decreasing from high to low priority Low priority interrupt Global Disable Individual Enable EXF2 TF2 TI RI TF0 INT0 INT1 TF1 IPH, IP IE0 0 3 0 3 0 3 0 3 0 3 |
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