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APA300-FGB Datasheet(PDF) 76 Page - Actel Corporation |
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APA300-FGB Datasheet(HTML) 76 Page - Actel Corporation |
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76 / 174 page  ProASICPLUS Flash Family FPGAs 1- 70 v5.7 Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Note: The plot shows the normal operation status. Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-64 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS ↓ 3.01 ns FCBA FULL ↓ access from RCLKS ↓ 3.01 ns ECBH, FCBH, THCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS ↓ 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete OCA New DO access from RCLKS ↑ 2.0 ns OCH Old DO valid from RCLKS ↑ 0.75 ns RDCH RDB hold from RCLKS ↑ 0.5 ns RDCS RDB setup to RCLKS ↑ 1.0 ns RPCA New RPE access from RCLKS ↑ 4.0 ns RPCH Old RPE valid from RCLKS ↑ 1.0 ns HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns. 2. All –F speed grade devices are 20% slower than the standard numbers. RCLK RPE RDATA EMPTY EQTH, GETH FULL Old Data Out New Valid Data Out RDB Cycle Start Old RPE Out New RPE Out tECBH, tFCBH tRDCH tRDCS tOCA tECBA, tFCBA tTHCBH tHCBA tCMH tCML tCCYC tRPCH tOCH tRPCA |
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