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RTAX250-SB624EV Datasheet(PDF) 46 Page - Actel Corporation

Part # RTAX250-SB624EV
Description  RTAX-S/SL RadTolerant FPGAs
Download  170 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RTAX250-SB624EV Datasheet(HTML) 46 Page - Actel Corporation

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RTAX-S/SL RadTolerant FPGAs
2- 28
v5.3
LVTTL I/O Module Drive Strength = 3 (16 mA) / High Slew Rate
tDP
Input buffer
1.85
2.17
ns
tPY
Output buffer
3.66
4.31
ns
tICLKQ
Clock-to-Q for the I/O input register
0.91
1.07
ns
tOCLKQ
Clock-to-Q for the IO output register and the I/O enable register
0.91
1.07
ns
tSUD
Data input setup
0.31
0.37
ns
tSUE
Enable input setup
0.35
0.41
ns
tHD
Data input hold
0.00
0.00
ns
tHE
Enable input hold
0.00
0.00
ns
tCPWHL
Clock pulse width High to Low
0.39
0.39
ns
tCPWLH
Clock pulse width Low to High
0.37
0.37
ns
tWASYN
Asynchronous pulse width
0.37
0.37
ns
tREASYN
Asynchronous recovery time
0.17
0.21
ns
tHASYN
Asynchronous removal time
0.00
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.31
0.37
ns
tPRESET
Asynchronous Preset-to-Q
0.31
0.37
ns
LVTTL I/O Module Drive Strength = 2 (12 mA) / High Slew Rate
tDP
Input buffer
1.85
2.17
ns
tPY
Output buffer
3.87
4.55
ns
tICLKQ
Clock-to-Q for the I/O input register
0.91
1.07
ns
tOCLKQ
Clock-to-Q for the IO output register and the I/O enable register
0.91
1.07
ns
tSUD
Data input setup
0.31
0.37
ns
tSUE
Enable input setup
0.35
0.41
ns
tHD
Data input hold
0.00
0.00
ns
tHE
Enable input hold
0.00
0.00
ns
tCPWHL
Clock pulse width High to Low
0.39
0.39
ns
tCPWLH
Clock pulse width Low to High
0.37
0.37
ns
tWASYN
Asynchronous pulse width
0.37
0.37
ns
tREASYN
Asynchronous recovery time
0.17
0.21
ns
tHASYN
Asynchronous removal time
0.00
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.31
0.37
ns
tPRESET
Asynchronous Preset-to-Q
0.31
0.37
ns
Table 2-22 • Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125°C (Continued)
Parameter
Description
'–1' Speed
'Std.' Speed
Units
Min.
Max.
Min.
Max.


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