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RTAX250-SB624EV Datasheet(PDF) 100 Page - Actel Corporation

Part # RTAX250-SB624EV
Description  RTAX-S/SL RadTolerant FPGAs
Download  170 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RTAX250-SB624EV Datasheet(HTML) 100 Page - Actel Corporation

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RTAX-S/SL RadTolerant FPGAs
2- 82
v5.3
Other Architectural Features
Charge Pump Bypass
To reduce power consumption, the internal charge pump
can be bypassed and an external power supply voltage
can be used instead. This saves the internal charge-pump
operating current, resulting in no DC current draw. The
RTAX-S/SL family devices have a dedicated "VPUMP" pin
that can be used to access an external charge pump
device. In normal chip operation, when using the
internal charge pump, VPUMP should be tied to GND.
When the voltage level on VPUMP is set to 3.3 V, the
internal charge pump is turned off, and the VPUMP
voltage will be used as the charge pump voltage.
Adequate voltage regulation (i.e., high drive, low output
impedance, and good decoupling) should be used at
VPUMP.
JTAG
RTAX-S/SL offers a JTAG interface that is compliant with
the IEEE 1149.1 standard except for the device ID length
which is 33 bits. The user can employ the JTAG interface
for probing a design and executing any JTAG public
instructions as defined in the Table 2-100. The JTAG pins
and probes are configured as a LVTTL standard port.
Refer to the IEEE Standard 1149.1 (JTAG) in the
Axcelerator Family application note, which also applies
to the RTAX-S/SL family of devices. The JTAG pins
should not be left floating on flight systems.
Interface
The interface consists of four inputs: Test Mode Select
(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller
Reset (TRST), and an output, Test Data Out (TDO). TMS,
TDI, and TRST have on-chip pull-up resistors.
TRST
TRST (Test-Logic Reset) is an active-low asynchronous
reset signal to the TAP controller. The TRST input can be
used to reset the Test Access Port (TAP) Controller to the
TRST state. The TAP Controller can be held at this state
permanently by grounding the TRST pin. To hold the
JTAG TAP controller in the TRST state, it is recommended
to connect TRST directly to ground for flight.
There is an optional internal pull-up resistor available for
the TRST input that can be set by the user at
programming. Care should be exercised when using this
option in combination with an external tie-off to
ground.
An on-chip power-on-reset (POWRST) circuit is included.
POWRST has the same function as "TRST," but it only
occurs at power-up or during recovery from a VCCA and/
or VCCDA voltage drop.
TDO
TDO is normally tristated, and it is active only when the
TAP controller is in the "Shift_DR" state or "Shift_IR"
state. The least significant bit of the selected register
(i.e., IR or DR) is clocked out to TDO first by the falling
edge of TCK.
TAP Controller
The TAP Controller is compliant with the IEEE Standard
1149.1. It is a state machine of 16 states that controls the
Instruction Register (IR) and the Data Registers (such as
Boundary-Scan Register, IDCODE, USRCODE, BYPASS,
etc.). The TAP Controller steps into one of the states
depending on the sequence of TMS at the rising edges of
TCK.
Instruction Register (IR)
The IR has five bits (IR4 to IR0). At the TRST state, IR is
reset to IDCODE. Each time when IR is selected, it goes
through "select IR-Scan," "Capture-IR," "Shift-IR," all the
way through "Update-IR." When there is no test error,
the first five data bits coming out of TDO during the
"Shift-IR" will be "10111." If a test error occurs, the last
three bits will contain one to three zeroes corresponding
to
negatively
asserted
signals:
"TDO_ERRORB,"
"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)
will be erased when the TAP is at the "Update-IR" or the
TRST state. When in user mode start-up sequence, if the
micro-probe has not been used, the "PROBA_ERRORB" is
used as a "Power-up done successfully" flag.
During flight, the following configurations for all JTAG
and Probe pins are recommended (Table 2-101 on
page 2-83).
Table 2-100 • JTAG Instruction Code
Instruction (IR4:IR0)
Binary Code
EXTEST
00000
PRELOAD / SAMPLE
00001
INTEST
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
DIAGNOSTIC
10000
Reserved
All others
BYPASS
11111


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