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A54SX08A-PQ208A Datasheet(PDF) 9 Page - Actel Corporation |
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A54SX08A-PQ208A Datasheet(HTML) 9 Page - Actel Corporation |
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9 / 68 page  v2.2 1-5 In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel’s segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-and-route software to minimize signal propagation delays. Clock Resources Actel’s high-drive routing structure provides three clock networks (Table 1-1). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinatorial logic. This provides a fast propagation path for the clock signal, enabling the 5.6 ns clock-to-out (pad-to-pad) performance of the auotmotive-grade SX-A devices. The hardwired clock is tuned to provide clock skew less than 0.3 ns worst case. If not used, this pin must be set as LOW or HIGH on the board. It must not be left floating. Figure 1-7 on page 1-6 describes the clock circuit used for the constant load HCLK. When the device is powered up and TRST is not grounded, HCLK does not function until the fourth clock cycle. This prevents possible false outputs due to a slow power-on-reset signal and fast start-up clock circuit. To activate HCLK from the first cycle, TRST pin must be reserved in the Designer software and the pin must be tied to GND on the board. Two additional clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the automotive-grade SX-A device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as LOW or HIGH on the board. They must not be left floating (except in the A54SX72A where these clocks can be configured as regular I/Os and can float). Figure 1-8 on page 1-6 describes the CLKA and CLKB circuit used in SX- A devices with the exception of A54SX72A. In addition to CLKA and CLKB, the A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD – corresponding to bottom-left, bottom-right, top-left, and top-right locations on the die, respectively), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. If QCLKs are not used as quadrant clocks, they will behave as regular I/Os. Bidirectional clock buffers are also available on the A54SX72A. The CLKA, CLKB, and QCLK circuits for A54SX72A are shown in Figure 1-9 on page 1- 6. Note that bidirectional clock buffers are only available in A54SX72A. For more information, refer to the “Pin Description” on page 1-38. For more information on how to use quadrant clocks in the A54SX72A device, refer to the Global Clock Networks in Actel’s Antifuse Devices and Using A54SX72A and RT54SX72S Quadrant Clocks application notes. Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters Type 2 SuperClusters Routing Segments • Typically 2 antifuses • Max. 5 antifuses FastConnect • One antifuse • 0.3 ns maximum routing delay DirectConnect • No antifuses • 0.1 ns maximum routing delay |
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