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RTAX250-SLB624E Datasheet(PDF) 57 Page - Actel Corporation |
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RTAX250-SLB624E Datasheet(HTML) 57 Page - Actel Corporation |
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57 / 170 page  RTAX-S/SL RadTolerant FPGAs v5.3 2-39 Class II AC Loadings Timing Characteristics Table 2-50 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA –0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.8 VREF+0.8 16 –16 Figure 2-25 • AC Test Loads Table 2-51 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-1.0 VREF+1.0 VREF 1.50 30 Note: *Measuring Point = Vtrip Test Point 30 pF 25 25 VTT Table 2-52 • Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125°C Parameter Description '–1' Speed 'Std.' Speed Units Min. Max. Min. Max. 3.3 V SSTL3 Class II I/O Module Timing tDP Input buffer 2.17 2.55 ns tPY Output buffer 2.55 2.99 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.37 0.37 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns |
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