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RTAX250-SS624E Datasheet(PDF) 15 Page - Actel Corporation |
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RTAX250-SS624E Datasheet(HTML) 15 Page - Actel Corporation |
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15 / 170 page  RTAX-S/SL RadTolerant FPGAs v5.3 1-7 Global Resources Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. Design Environment The RTAX-S/SL family of FPGAs is fully supported by both Actel Libero® Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Actel website). Libero IDE includes Synplify® AE from Synplicity®, ViewDraw® AE from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from SynaptiCAD®, and Designer software from Actel. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: • Timer – a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route • NetlistViewer – a design netlist schematic viewer • ChipPlanner – a graphical floorplanner viewer and editor • SmartPower – allows the designer to quickly estimate the power consumption of a design • PinEditor – a graphical application for editing pin assignments and I/O attributes • I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, the Actel back- annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, the Actel integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Actel Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI. Factory programming is available for high- volume production needs. Low-Cost Prototyping Solutions Since the enhanced radiation characteristics of radiation- tolerant devices are not required during the prototyping phase of the design, Actel has developed two prototyping options for RTAX-S/SL. For early design development and functional verification, Actel offers the commercial Axcelerator devices while for final flight design verification in hardware, Actel offers the RTAX-S PROTO device that has the same form, fit, and function as the flight silicon. Prototyping with Axcelerator Units The prototyping solution using the commercial Axcelerator devices consists of two parts: • A well-documented design flow that allows the customer to target an RTAX-S/SL design to the equivalent commercial Axcelerator device • A set of Actel Extender circuit boards that map the commercial device package to the appropriate RTAX-S package footprint This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Actel FPGAs. Prototyping with RTAX-S PROTO Units The RTAX-S PROTO units offer a prototyping solution that can be used for final timing verification of the flight design. The RTAX-S PROTO prototype units have the same timing attributes as the RTAX-S/SL flight units. Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in their part number, and “PROTO” is marked on devices to indicate that they are not intended for space flight. They also are not intended for applications, which require the quality of space-flight units, such as qualification of space-flight hardware. RT-PROTO units offer no guarantee of hermeticity, and no MIL-STD-883B processing. At a minimum, users should plan on using class B level devices for all qualification activities. |
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