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RTAX250-SS624E Datasheet(PDF) 92 Page - Actel Corporation |
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RTAX250-SS624E Datasheet(HTML) 92 Page - Actel Corporation |
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92 / 170 page  RTAX-S/SL RadTolerant FPGAs 2- 74 v5.3 Figure 2-53 illustrates flag generation. The Verilog statements for flag assignment are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-92). The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-77. For more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller. Figure 2-53 • ALMOST-EMPTY and ALMOST-FULL Logic Table 2-92 • Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 11x1 4 21x2 4 22x1 5 41x4 4 42x2 5 44x1 6 81x8 4 82x4 5 84x2 6 88x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 WCNTR [15:0] WCLK RCNTR [15:0] RCLK 16 16 X Y X Y AEMPTY AFULL X>=Y (16-bit) DIFF [15:0] AEVAL [7:0], GND [7:0] (MSB....LSB) AFVAL [7:0], GND [7:0] (MSB....LSB) |
Similar Part No. - RTAX250-SS624E |
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Similar Description - RTAX250-SS624E |
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