 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
RTAX250-SLS624B Datasheet(PDF) 13 Page - Actel Corporation |
|
||||||||||||||||||||||||||||||
RTAX250-SLS624B Datasheet(HTML) 13 Page - Actel Corporation |
|
|
13 / 170 page  RTAX-S/SL RadTolerant FPGAs v5.3 1-5 Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspect- ratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. The FIFO control unit was not implemented with SEU- hardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. Actel has enhanced the SEU tolerance of the embedded SRAM within RTAX-S/SL by employing the use of two upset-mitigation techniques: • Actel has developed Error Detection and Correction (EDAC) IP for use with RTAX-S/SL. EDAC can be accomplished by the use of SmartGen-generated Error Correcting Codes (ECC) IP, which employs the use of shortened Hamming Codes • A background memory-refresher, or scrubber circuitry, which has been embedded into the EDAC IP. The embedded scrubber circuitry periodically refreshes memory in the background to ensure that no data corruption occurs while the memory is not in use. The use of EDAC IP combined with the embedded memory scrubber circuitry, gives the RTAX-S/SL an SEU radiation performance level of better than 10-10 errors/ bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. I/O Logic The RTAX-S/SL family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5 V, 1.8 V, 2.5 V, and 3.3 V. In all, RTAX-S/SL FPGAs support at least 14 different I/O standards (single-ended, differential, voltage- referenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-12 for more information). All I/O standards are available in each bank. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-6). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. By design, all user flip-flops in the RTAX-S FPGAs are immune to SEUs including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. Routing The RTAX-S/SL hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the carry-logic FCO output of one C-cell pair to the carry-logic FCI input of the C-cell pair of the SuperCluster below. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. |
Similar Part No. - RTAX250-SLS624B |
|
Similar Description - RTAX250-SLS624B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
