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RTAX250-SLS624B Datasheet(PDF) 81 Page - Actel Corporation

Part # RTAX250-SLS624B
Description  RTAX-S/SL RadTolerant FPGAs
Download  170 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RTAX250-SLS624B Datasheet(HTML) 81 Page - Actel Corporation

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RTAX-S/SL RadTolerant FPGAs
v5.3
2-63
Embedded Memory
The RTAX-S/SL architecture provides extensive, high-
speed memory resources to the user. Each 4,608-bit block
of RAM contains its own embedded FIFO controller,
allowing the user to configure each block as either RAM
or FIFO.
To meet the needs of high performance designs, the
memory blocks operate in synchronous mode for both
read and write operations. However, the read and write
clocks are completely independent, and each may
operate beyond 500 MHz.
No additional core logic resources are required to
cascade the address and data buses when cascading
different RAM blocks. Dedicated routing runs along each
column of RAM to facilitate cascading.
The RTAX-S/SL memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and
write operations can occur asynchronously to one another,
special
control
circuitry
is
included
to
prevent
metastability, overflow, and underflow. A block diagram
of the memory module is illustrated in Figure 2-48.
During RAM operation, read (RA) and write (WA)
addresses are sourced by user logic and the FIFO
controller is ignored. In FIFO mode, the internal
addresses are generated by the FIFO controller and
routed to the RAM array by internal MUXes. Enables
with programmable polarity are provided to create
upper address bits for cascading up to 16 memory blocks.
When cascading memory blocks, the bussed signals WA,
WD, WEN, RA, RD, and REN are internally linked to
eliminate external routing congestion.
RAM
Each memory block consists of 4,608 bits that can be
organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1
and are cascadable to create larger memory sizes. This
allows built-in bus width conversion (Table 2-82). Each
block has independent read and write ports, which
enable
simultaneous
read
and
write
operations.
Simultaneous read and write operations to the same
address is not supported.
Figure 2-48 • RTAX-S/SL Memory Module
RA [K:0]
RD [(N-1):0]
REN
RCLK
WD [(M-1):0]
WA [J:0]
WEN
WCLK
PIPE
RW [2:0]
WW [2:0]
Table 2-82 • Memory Block WxD Options
Data-Word (in bits)
Depth
Address Bus
Data Bus
1
4,096
RA/WA[11:0]
RD/WD[0]
2
2,048
RA/WA[10:0]
RD/WD[1:0]
4
1,024
RA/WA[9:0]
RD/WD[3:0]
9
512
RA/WA[8:0]
RD/WD[8:0]
18
256
RA/WA[7:0]
RD/WD[17:0]
36
128
RA/WA[6:0]
RD/WD[35:0]


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