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RTAX250-SS624B Datasheet(PDF) 38 Page - Actel Corporation |
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RTAX250-SS624B Datasheet(HTML) 38 Page - Actel Corporation |
38 / 170 page RTAX-S/SL RadTolerant FPGAs 2- 20 v5.3 User I/O Naming Conventions Due to the complex and flexible nature of the RTAX-S/SL family’s user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7). Figure 2-7 • I/O Bank and Dedicated Pin Layout Figure 2-8 • General Naming Schemes Corner4 Corner3 Corner1 I/O BANK 0 I/O BANK 5 I/O BANK 1 I/O BANK 4 Corner2 RTAX-S/SL GND V CCDA GND V CCDA GND V CCDA GND V CCDA GND V CCDA GND V CCA GND V CCA GND V CCA GND V CCA GND V CCI 2 GND V CCDA GND V CCI 6 GND V CCI 7 GND V CCI 3 IOxxXBxFx Fx refers to an unimplemented feature and can be ignored Bank I/D 0 through 7, clockwise from IOB NW P - Positive Pin/ N- Negative Pin Pair number in the bank, starting at 00, clockwise from IOB NW IO12PB1F1 Is the positive pin of the thirteenth pair of the first I/O bank (IOB NE). IO12PB1 combined with IO12NB1 form a differential pair. For those I/Os that can be employed either as a user I/O or as a special function, the following nomenclature is used: IOxxXBxFx/special_function_name IOxxPB1Fx/CLKx This pin can be configured as a clock input or as a user I/O Examples: |
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