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RTAX250-SS624B Datasheet(PDF) 35 Page - Actel Corporation |
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RTAX250-SS624B Datasheet(HTML) 35 Page - Actel Corporation |
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35 / 170 page  RTAX-S/SL RadTolerant FPGAs v5.3 2-17 Customizing the I/O RTAX-S/SL I/O slew-rates and drive strength can be customized: • The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. • The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values—8 mA, 12 mA, 16 mA, or 24 mA—that can be specified in Designer.5 Using the Differential I/O Standards Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Note that there are no tristated or bidirectional I/O buffers for differential standards. Using the Voltage-Referenced I/O Standards Using these I/O standards is similar to that of single- ended I/O standards. Their settings can be changed in Designer. Using DDR (Double Data Rate) In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very high- speed systems. To implement a DDR, users must do the following: 1. Instantiate an input buffer (with the required I/O standard). 2. Instantiate the DDR_REG macro (Figure 2-6). 3. Connect the output from the Input buffer to the input of the DDR macro. 4. DDR supports all I/O standards. 5. The DDR macro in SmartGen can be used to implement DDR. 6. Bit width and I/O standard can be chosen in SmartGen. Macros for Specific I/O Standards There are different macro types for any I/O standard or feature that determine the required VCCI and VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and 24 mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals. Most of the macro symbols represent variations of the six generic symbol types: • CLKBUF: Clock Buffer • HCLKBUF: Hardwired Clock Buffer • INBUF: Input Buffer • OUTBUF: Output Buffer • TRIBUF: Tristate Buffer • BIBUF: Bidirectional Buffer Other macros include the following: • Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). • Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. • DDR_REG macro. It can be connected to any I/O standard input buffers (i.e., INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module. 5. These values are minimum drive strengths. Figure 2-6 • DDR Register DQR QF E CLR PRE CLK |
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Similar Description - RTAX250-SS624B |
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