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RTAX250-SLG624B Datasheet(PDF) 99 Page - Actel Corporation |
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RTAX250-SLG624B Datasheet(HTML) 99 Page - Actel Corporation |
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99 / 170 page  RTAX-S/SL RadTolerant FPGAs v5.3 2-81 Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: • Using the SmartGen core generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (please refer to the Actel SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide for more information). • The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. Table 2-99 • Sixteen FIFO Blocks are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125°C) Parameter Description '–1' Speed 'Std' Speed Units Min. Max. Min. Max. FIFO Module Timing tWSU Write Setup 22.14 26.03 ns tWHD Write Hold 0.30 0.35 ns tWCKH WCLK High 1.31 1.54 ns tWCKL WCLK Low 23.34 27.44 ns tWCKP Minimum WCLK Period tRSU Read Setup 24.27 28.53 ns tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 1.27 1.49 ns tRCKL RCLK Low 25.10 29.51 ns tRCKP Minimum RCLK period tCLRHF Clear High 1.45 1.70 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 7.94 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 17.02 20.01 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 18.62 21.89 ns |
Similar Part No. - RTAX250-SLG624B |
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