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RTSX72SU-1CQ256M Datasheet(PDF) 7 Page - Actel Corporation |
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RTSX72SU-1CQ256M Datasheet(HTML) 7 Page - Actel Corporation |
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7 / 83 page  RTSX-SU RadTolerant FPGAs (UMC) v2.2 1-1 General Description RTSX-SU RadTolerant FPGAs are enhanced versions of Actel’s SX-A family of devices, specifically designed for enhanced radiation performance. Featuring SEU-hardened D-type flip-flops that offer the benefits of Triple Module Redundancy (TMR) without the associated overhead, the RTSX-SU family is a unique product offering for space applications. Manufactured using 0.25 µm technology at the United Microelectronics Corporation (UMC) facility in Taiwan, RTSX-SU offers levels of radiation survivability far in excess of typical CMOS devices. Device Architecture Actel's RTSX-SU architecture, derived from the highly successful SX-A sea-of-modules architecture, has been designed to improve upset and total-dose performance in radiation environments. With three layers of metal interconnect in the RTSX32SU and four metal layers in RTSX72SU, the RTSX-SU family provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers. This completely eliminates the channels of routing and interconnect resources between logic modules as found in traditional FPGAs. In a sea-of-modules architecture, the entire floor of the FPGA is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. The RTSX-SU architecture adds several enhancements over the SX-A architecture to improve its performance in radiation environments, such as SEU-hardened flip-flops, wider clock lines, and stronger clock drivers. Programmable Interconnect Elements Interconnection between logic modules is achieved using Actel’s patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuit and form a permanent, low-impedance connection when programmed. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed (“on” state) resistance of 25 Ω with capacitance of 1.0 fF for low signal impedance (Figure 1-1 on page 1-2). These antifuse interconnects reside between the top two layers of metal and thereby enable the sea-of-modules architecture in an FPGA. The extremely small size of these interconnect elements gives the RTSX-SU family abundant routing resources and provides excellent protection against design theft. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. Additionally, since RTSX-SU is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. The RTSX-SU interconnect (i.e., the antifuses and metal tracks) also has lower capacitance and resistance than that of any other device of similar capacity, leading to the fastest signal propagation in the industry for the radiation tolerance offered. I/O Structure The RTSX-SU family features a flexible I/O structure that supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V PCI. All I/O standards are hot-swap compliant, cold- sparing capable, and 5V tolerant (except for 3.3V PCI). In addition, each I/O on an RTSX-SU device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards are allowed and can be set on a pin-by-pin basis. High or low slew rate can be set on individual output buffers (except for PCI, which defaults to high slew), as well as the power-up configuration (either pull-up or pull-down). Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-output-pad timing as fast as 9.5 ns. In most FPGAs, I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in RTSX-SU FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn, enables parallel design of system components and reduces overall design time. |
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