Verification and Compliance

Functional and timing simulation has been performed on the MultiChannel UART using a self-checking Verilog Test Bench with Verilog test cases.

Timing

The timing diagrams below reflect ads_n held active, or low.

Since this IP is a core, the effects of part speed grade, family, routing variations, and effects of user logic in placement and routing will have varying degrees of impact

on the timing. The user must take these things in consideration to insure a successful implementation. The Timing information provided in this document, will ad-

dress timing requirements based upon architectural aspects of this IP only.

READ TIMING

The figure below shows the setup times required for a successful read. It also shows the expected delay between the assertion of the rd_n signal, and valid data on

the bus. The data remains valid as long as A, cs_n, and rd_n are held in their active states.

Figure 3: Asynchronous Timing For Reads

Description

Min

Max

Setup time for cs_n with respect to rd_n

Setup time for A with repect to rd_n

Hold time for CS with respect to rd_n

Hold time for A with respect to rd_n

Delay between rd_n assertion (going low) and valid data on the bus

rd_n strobe width

Table 4: Read Timing Descriptions

Where:

• NUM_CHANNELS is the number of ports selected of the implementation

the width of the rd_n signal accordingly.

cs_n

rd_n

data_out

A

Data Valid

wr_n