VME2416

Memec Design

February 25, 2003

3

Optimized for

Functional Description

The falling edge of VME_AS (address strobe) will synchronize all the addresses (VME_ADDR and VME_AM)

allowing the controller to decode them in order to define if the present board is addressed or not. Since this

moment, all signals on the VME bus have to be stable and the controller will execute the command depending on

the control signals (VME_DS0_N, VME_DS1_N, VME_WRITE_N, VME_IACK_N). The VME master has to release

the VME_AS_N signal at the end of a transfer to execute a new command.

WRITE DATA TRANSFER

When the VME_WRITE_N defines a write data transfer, the controller will assign the address (VME_ADDR) on the

USER_ADDR bus, the address modifier (VME_AM) on the USER_AM bus and the data (VME_DATA) on the

USER_DATA bus. The signals VME_DS0_N and VME_DS1_N select the corresponding data location according

the following table (for this model of VME controller-MC-ACT-VME2416-, the signals VME_LWORD and

VME_ADDR01 are don’t care):

Data Locations Selected

VME_DS0_N

VME_DS1_N

VME_ADDR01

VME_LWORD_N

VME_DATA_IN(7:0)

VME_DATA_IN(15:8)

low

high

high

low

X

X

X

X

VME_DATA_IN(15:0)

low

low

X

X

To execute the transfer on the user part, the controller will active a request signal (USER_ACC_REQ) with valid

control signals. The data locations selected are enabled with the signals USER_BE1 (bits 7:0) and USER_BE2 (bits

15:8). The transfer will be ended with the acknowledge of the user part (USER_ACC_ACK).

Once the transfer executed, the controller will acknowledge the data transfer on the VME bus with the

VME_DTACK_N. When seeing this acknowledge, the master will release the VME_AS_N signal ending the actual

data transfer.

READ DATA TRANSFER

When the VME_WRITE_N defines a read data transfer, the controller will assign the address (VME_ADDR) on the

USER_ADDR bus and the address modifier (VME_AM) on the USER_AM bus. As the write data transfer, the

signals USER_BE1/2 are depending on the VME_DS0/1_N.

The controller will active a request signal (USER_ACC_REQ) until the acknowledge (USER_ACC_ACK) coming

from the user part. The read data have to be valid during this acknowledge.

Once ready, the data are transferred on the VME_DATA_OUT bus and acknowledged with the signal

VME_DTACK_N. When seeing this acknowledge, the master will release the VME_AS_N signal ending the actual

data transfer.

INTERRUPT

The interrupts on the VME bus are generated by the different modules connected on the bus and are acknowledged

through a daisy-chain interrupt line as shown on the figure below:

Memory Board

(user part)

IO Board

(user part)

Interrupt

Handler

MC-ACT-

VME

MC-ACT-

VME

VME

Interface

iack_n