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## AGL1000V2-FGG144I Datasheet(PDF) 30 Page - Actel Corporation

 Part No. AGL1000V2-FGG144I Description IGLOO Low-Power Flash FPGAs with Flash Freeze Technology Download 212 Pages Scroll/Zoom 100% Maker ACTEL [Actel Corporation] Homepage http://www.actel.com Logo

## AGL1000V2-FGG144I Datasheet(HTML) 30 Page - Actel Corporation

 30 / 212 page IGLOO DC and Switching Characteristics2- 16Advance v0.5Power Calculation MethodologyThis section describes a simplified method to estimate power consumption of an application. Formore accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDEsoftware.The power calculation methodology described below uses the following variables:•The number of PLLs as well as the number and the frequency of each output clockgenerated•The number of combinatorial and sequential cells used in the design•The internal clock frequencies•The number and the standard of I/O pins used in the design•The number of RAM blocks used in the design•Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 onpage 2-18.•Enable rates of output buffers—guidelines are provided for typical applications inTable 2-23 on page 2-18.•Read rate and write rate to the memory—guidelines are provided for typical applications inTable 2-23 on page 2-18. The calculation should be repeated for each clock domain definedin the design.MethodologyTotal Power Consumption—PTOTALPTOTAL = PSTAT + PDYNPSTAT is the total static power consumption.PDYN is the total dynamic power consumption.Total Static Power Consumption—PSTATPSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7NINPUTS is the number of I/O input buffers used in the design.NOUTPUTS is the number of I/O output buffers used in the design.NBANKS is the number of I/O banks powered in the design.Total Dynamic Power Consumption—PDYNPDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLLGlobal Clock Contribution—PCLOCKPCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLKNSPINE is the number of global spines used in the user design—guidelines are providedin Table 2-22 on page 2-18.NROW is the number of VersaTile rows used in the design—guidelines are provided inTable 2-22 on page 2-18.FCLK is the global clock signal frequency.NS-CELL is the number of VersaTiles used as sequential modules in the design.PAC1, PAC2, PAC3, and PAC4 are device-dependent.Sequential Cells Contribution—PS-CELLPS-CELL = NS-CELL * (PAC5 +α1 / 2 * PAC6) * FCLKNS-CELL is the number of VersaTiles used as sequential modules in the design. When amulti-tile sequential cell is used, it should be accounted for as 1.α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 onpage 2-18.FCLK is the global clock signal frequency.

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