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AGL1000V2-FGG144I Datasheet(PDF) 92 Page - Actel Corporation

Part No. AGL1000V2-FGG144I
Description  IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
Download  212 Pages
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Maker  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
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AGL1000V2-FGG144I Datasheet(HTML) 92 Page - Actel Corporation

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IGLOO DC and Switching Characteristics
2- 78
Advance v0.5
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-22 • Input DDR Timing Diagram
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRICLR2Q1
12
3
4
5
6
7
8
9
CLK
Data
CLR
Out_QR
Out_QF
tDDRICLKQ1
2
4
6
3
5
7
tDDRIHD
tDDRISUD
tDDRICLKQ2
Table 2-144 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.25 V
Parameter
Description
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.48
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.65
ns
tDDRISUD1
Data Setup for Input DDR (negedge)
0.50
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
0.40
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
0.00
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.82
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.98
ns
tDDRIREMCLR
Asynchronous Clear Removal Time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.23
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.19
ns
tDDRICKMPWH
Clock Minimum Pulse Width HIGH for Input DDR
0.31
ns
tDDRICKMPWL
Clock Minimum Pulse Width LOW for Input DDR
0.28
ns
FDDRIMAX
Maximum Frequency for Input DDR
TBD
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.


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