Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AGL1000V2-FGG144I Datasheet(PDF) 90 Page - Actel Corporation

Part No. AGL1000V2-FGG144I
Description  IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
Download  212 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
Logo ACTEL - Actel Corporation

AGL1000V2-FGG144I Datasheet(HTML) 90 Page - Actel Corporation

Back Button AGL1000V2-FGG144I Datasheet HTML 86Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 87Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 88Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 89Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 90Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 91Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 92Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 93Page - Actel Corporation AGL1000V2-FGG144I Datasheet HTML 94Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 90 / 212 page
background image
IGLOO DC and Switching Characteristics
2- 76
Advance v0.5
1.2 V DC Core Voltage
Table 2-142 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tOECLKQ
Clock-to-Q of the Output Enable Register
1.10
ns
tOESUD
Data Setup Time for the Output Enable Register
1.15
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
1.22
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
1.65
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
1.65
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH
Clock Minimum Pulse Width HIGH for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn