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AGL1000V2-FGG144I Datasheet(PDF) 89 Page - Actel Corporation

Part No. AGL1000V2-FGG144I
Description  IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
Download  212 Pages
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Maker  ACTEL [Actel Corporation]
Homepage  http://www.actel.com
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AGL1000V2-FGG144I Datasheet(HTML) 89 Page - Actel Corporation

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IGLOO DC and Switching Characteristics
Ad vance v0.5
2-75
Output Enable Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-20 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
tOESUE
50%
50%
tOESUD tOEHD
50%
50%
tOECLKQ
1
0
tOEHE
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
Table 2-141 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.75
ns
tOESUD
Data Setup Time for the Output Enable Register
0.51
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.73
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
1.13
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
1.13
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH
Clock Minimum Pulse Width HIGH for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.


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