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AGL1000V2-FGG144I Datasheet(PDF) 84 Page - Actel Corporation |
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AGL1000V2-FGG144I Datasheet(HTML) 84 Page - Actel Corporation |
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84 / 212 page 
IGLOO DC and Switching Characteristics 2- 70 Advance v0.5 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear CLK Enable CLR Data_out Data Y AA EOUT DOUT Core Array DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR BB CC DD EE FF GG LL HH JJ KK INBUF INBUF CLKBUF Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered |
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