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AGL1000V2-FGG144I Datasheet(PDF) 82 Page - Actel Corporation |
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AGL1000V2-FGG144I Datasheet(HTML) 82 Page - Actel Corporation |
82 / 212 page ![]() IGLOO DC and Switching Characteristics 2- 68 Advance v0.5 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF CLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered CLK Enable Preset Data_out Data EOUT DOUT DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE A B C D E E E E F G H I J L K Y Core Array |