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AGL1000V2-FGG144I Datasheet(PDF) 7 Page - Actel Corporation

Part No. AGL1000V2-FGG144I
Description  IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
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Maker  ACTEL [Actel Corporation]
Homepage  http://www.actel.com

AGL1000V2-FGG144I Datasheet(HTML) 7 Page - Actel Corporation

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IGLOO Low-Power Flash FPGAs
1 - 3
external memory components; instead it retains all necessary information to resume operation
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device
architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO
family a cost-effective ASIC replacement solution, especially for applications in the consumer,
networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-
based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot
be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error
detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic
utilization without compromising device routability or performance. Logic functions within the
device are interconnected through a four-level routing hierarchy.
IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The
IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on
page 1-4 and Figure 1-2 on page 1-4):
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs†
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup
table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.
The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture
flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
The AGL015 and AGL030 do not support PLL or SRAM.

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