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CORE429-UR Datasheet(PDF) 4 Page - Actel Corporation

Part # CORE429-UR
Description  ARINC 429 Bus Interface
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

CORE429-UR Datasheet(HTML) 4 Page - Actel Corporation

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ARINC 429 Bus Interface
4
v5.0
Core429 clock rate can be programmed to be 1, 10, 16, or
20 MHz. All the Actel families listed above easily meet
the required performance.
Core429 I/O requirements depend on the system
requirements and the external interfaces. If the core and
memory blocks are implemented within the FPGA and
the CPU interface has a bidirectional data bus, then
approximately 74 I/O pins are required to implement
four Rx and four Tx modules. The core will require 62
pins to implement one Rx and one Tx module.
The core has various FIFO flags available for debugging
purposes. These flags may not be needed in the final
design and this will reduce the I/O count.
Memory Requirements
The number of memory blocks required differs, depending on whether each channel is configured the same or
differently.
Each Channel Configured the Same
Use EQ 1 to calculate the number of memory blocks required if each channel is configured the same.
Number of memory blocks = NRx * (INT (LABEL_SIZE/X) + INT (RX_FIFO_DEPTH/Y) + NTx * INT (FIFO_DEPTH/Y),
EQ 1
Table 3 •
Device Utilization for One Rx and One Tx Module
Cells or Tiles
Family
Combinatorial
Sequential
Total
Memory Blocks
Device
Utilization
Fusion
848
609
1,457
3
AFS600
10%
ProASIC3/E
848
609
1,457
3
A3PE600
10%
ProASICPLUS
1,084
377
1,461
3
APA075
48%
Axcelerator
518
378
896
3
AX125
44%
RTAX-S
604
429
1,033
3
RTAX250S
24%
Table 4 •
Device Utilization for 16 Rx and 16 Tx Modules
Cells or Tiles
Family
Combinatorial
Sequential
Total
Memory Blocks
Device
Utilization
Fusion
13,435
9,614
23,049
48
AFS1500
60%
ProASIC3/E
13,435
9,614
23,049
48
A3PE1500
60%
ProASICPLUS
16,835
5,928
22,763
48
APA750
69%
Axcelerator
8,044
5,944
13,988
48
AX2000
43%
RTAX-S
9,594
6,745
16,339
48
RTAX2000S
51%
Table 5 •
Device Utilization for Legacy Mode (2 Rx and 1 Tx)
Family
Cells or Tiles
Memory
Blocks
Device
Utilization
Combinational
Sequential
Total
Fusion
1,444
1,068
2,512
5
AFS600
18%
ProASIC3/E
1,444
1,068
2,512
5
A3PE600
18%
ProASICPLUS
1,840
674
2,514
5
APA150
41%
Axcelerator
955
653
1,608
5
RTAX250S
20%
RTAX-S
1,062
729
1,791
5
RTAX250S
42%


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