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CORE429-AR Datasheet(PDF) 7 Page - Actel Corporation |
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CORE429-AR Datasheet(HTML) 7 Page - Actel Corporation |
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7 / 22 page  ARINC 429 Bus Interface v5.0 7 Figure 5 gives a functional description of the Tx block. The Tx module converts the 32-bit parallel data from the TX FIFO to serial data. It also inserts the parity bit into the ARINC data when parity is enabled. The CPU interface is used to fill the FIFO with ARINC data. The TX FIFO can hold up to 512 ARINC words of data. The transmission starts as soon as one complete ARINC word has been stored in the transmit FIFO. The Tx module contains two 8-bit registers. One is used for a control function and the other is used for status. The CPU interface allows the system CPU to access the control and status registers within the core. The TX FIFO asserts three status signals: • tx_fifo_empty: TX FIFO is empty • tx_fifo_half_full: TX FIFO is filled up to the programmed TX_FIFO_LEVEL • tx_fifo_full: TX FIFO is full Depending on the FIFO status signals, the CPU will either read the FIFO before it overflows, or not attempt to read the FIFO if it is empty. The interrupt signal int_out_tx is generated when one of the FIFO status signals (tx_fifo_empty, tx_fifo_half_full and tx_fifo_full) are high. Legacy Mode In this mode, there is a legacy interface block that communicates with the CPU interface. When legacy mode is enabled, the core supports two receive (Rx) channels and one transmit (Tx) channel only. This is not configurable. Figure 5 • Core429 Tx Block Diagram 32-Bit Parallel- to-Serial Register Control Logic Control Reg Status Reg CPU I/F Parity Generator FIFO clk cpu_add cpu_wen cpu_ren cpu_din cpu_dout cpu_wait Waveform Shaper RxLo RxHi Load Shift |
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