Core8051

4

v6.0

Core8051 Device Requirements

Core8051 has been implemented in several of the Actel device families. A summary of the implementation data is

listed in Table 2 through Table 4. Table 2 lists implementation data without OCI logic.

Table 3 lists implementation data with OCI logic (no trace memory and no hardware triggers).

Table 4 lists implementation data with OCI logic (256-word trace memory and one hardware trigger).

Table 2 • Core8051 Device Utilization and Performance - No OCI

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

RAM Blocks

Device

Total

Fusion

528

3629

4157

1

AFS600

30%

36 MHz

ProASIC3/E

528

3629

4157

1

A3PE600-2

30%

36 MHz

528

3909

4437

1

APA150-STD

72%

24 MHz

Axcelerator

619

2344

2963

1

AX250-3

70%

52 MHz

RTAX-S

619

2344

2963

1

RTAX1000S-1

16%

29 MHz

SX-A

646

2780

3426

-

A54SX72A-3

57%

33 MHz

RTSX-S

646

2780

3426

-

RT54SX72S-1

57%

19 MHz

Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro

alone.

Table 3 • Core8051 Device Utilization and Performance - OCI without Trace Memory and Hardware Trigger

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

RAM Blocks

Device

Total

Fusion

621

3923

4544

1

AFS600

33%

33 MHz

ProASIC3/E

621

3923

4544

1

A3PE600-2

33%

33 MHz

621

4249

4870

1

APA150-STD

79%

20 MHz

Axcelerator

739

2646

3385

1

AX500-3

42%

44 MHz

RTAX-S

739

2646

3385

1

RTAX1000S-1

19%

25 MHz

SX-A

765

2914

3679

-

A54SX72A-3

61%

29 MHz

RTSX-S

765

2914

3679

-

RT54SX72S-1

61%

19 MHz

Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro

alone.

Table 4 • Core8051 Device Utilization and Performance - OCI with 256-Word Trace Memory and One Hardware Trigger

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

RAM Blocks

Device

Total

Fusion

718

4323

5041

3

AFS600

37%

33 MHz

ProASIC3/E

718

4323

5041

3

A3PE600-2

37%

33 MHz

717

4709

5426

4

APA150-STD

88%

20 MHz

Axcelerator

843

3023

3866

3

AX500-3

48%

40 MHz

RTAX-S

843

3023

3866

3

RTAX1000S-1

21%

24 MHz

Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro

alone.