CoreU1LL UTOPIA Level 1 Link-Layer Interface

v4.0

3

cell, the CoreU1LL PHY-Layer device sends cells back-to-

back (Figure 4 on page 3).

Rx Interface (Ingress)

The Rx interface operates in a similar manner to the Tx

interface. The PHY-Layer device indicates that it has a cell

ready to transfer by asserting u1_rx_clav high. Then, the

user interface is ready to accept a cell (w_avail high). The

CoreU1LL will initiate a transfer on the Rx interface by

asserting u1_rx_en low (Figure 5).

The PHY-Layer device then asserts u1_rx_soc high,

indicating that the first word of the cell transfer is active

on the bus. Once a transfer has begun, all 53 or 54 bytes

of the cell are transferred without interruption.

If polling during the current transfer indicates that there

are no more cells available, or if the CoreU1LL is unable

to accept another cell from the PHY-Layer device, the

CoreU1LL deselects the physical interface by deasserting

u1_rx_en after receiving the last byte of the current cell,

as illustrated in Figure 6.

If the user interface continues to assert w_avail during

the last two bytes of the current cell transfer, and one or

more complete ATM cells are ready to be transferred

(u1_rx_clav is high), the CoreU1LL accepts back-to-back

cells, as shown in Figure 7.

User Interface

The user interface can connect directly to Actel's

CoreATMBUF3 cell buffer, an intellectual property core

that provides buffering for up to three, 54-byte ATM

cells in each direction (Figure 1 on page 1). Alternatively,

the designer may connect his/her own cell buffer or user

logic function directly to the user interface. The signals

associated with the user interface are summarized in

Table 3.

When reset is asserted high, all registers in the CoreU1LL

are cleared. They will remain in this state as long as reset

is asserted.

If the xlate input is low, the CoreU1LL transfers data to/

from the PHY-Layer device as 53-byte ATM cells. On

ingress (Rx), the CoreU1LL will duplicate the fifth byte of

the ATM header and insert it as the sixth byte (UDF2) in

order to create a standard 54-byte ATM cell on the user

Figure 4 • Tx Back-to-Back Transfer

Figure 5 • Rx Start of Cell Transfer

Figure 6 • Rx End of Transfer

U1_tx_clk

U1_tx_clav

U1_tx_en

U1_tx_soc

U1_tx_data

P51 P52 P53 P54

H1

H2

H3

H4

H5

H6

H1 H2

u1_rx_clk

u1_rx_clav

u1_rx_en

u1_rx_soc

u1_rx_data

P51 P52 P53 P54

XX

u1_rx_clk

u1_rx_clav

u1_rx_en

u1_rx_soc

u1_rx_data

Figure 7 • Rx Back-to-Back Transfer

Table 3 • User Interface Signals

Signal

Type Description

reset

In

Active high – resets all registers

xlate

In

53- / 54-byte cell size control

w_avail

In

Active high – user ready to receive

w_phy_act

Out

Active high physical selected

w_enable

Out

Active high data enable

w_adr

Out

5-bit word count

w_data

Out

16-bit data bus

r_avail

In

Active high – user ready to send

r_buf_en

Out

Active high read enable

r_adr

Out

5-bit word count

r_data

In

16-bit data bus

P51 P52 P53 P54

H1

H2

H3

H4

H5

U1_rx_clk

U1_rx_clav

U1_rx_en

U1_rx_soc

U1_rx_data