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COREU1PHY-EV Datasheet(PDF) 5 Page - Actel Corporation |
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COREU1PHY-EV Datasheet(HTML) 5 Page - Actel Corporation |
5 / 8 page CoreU1PHY – UTOPIA Level 1 PHY Interface v4.0 5 Read Interface (egress) When r_avail is asserted high at the user interface and the u1_rx_en signal is asserted low by the link-layer, the CoreU1PHY will begin accepting data on the user interface. Once a cell transfer has begun, the CoreU1PHY will transfer 27 words of data regardless of the state of r_avail. The CoreU1PHY asserts r_buf_en high, expecting to accept data at the r_data inputs on the next rising- edge of u1_rx_clk as illustrated in Figure 10. The CoreU1PHY provides r_adr as a word count (00 to 1B hex) and increments whenever the core accepts data at the r_data pins. Since the CoreU1PHY translates from 16- bit data at the user interface to 8-bit data at the UTOPIA interface, r_buf_en is asserted for one clock cycle, data is accepted on the following rising edge of u1_rx_clk, and the r_adr is incremented. Then r_buf_en is de-asserted for one clock cycle except after the third data word when xlate is low (53-byte mode), or when a back-to-back read operation is needed in order to get the first payload byte in time. The cycle is repeated until r_adr reaches 1B hex and the last two bytes of the ATM cell are sent. At this point, r_adr is reset to 00 hex, and if r_avail indicates that another cell is immediately available, and u1_rx_en remains low, the CoreU1PHY will immediately begin sending the next cell as shown in Figure 11. Otherwise, r_buf_en remains low until the CoreU1PHY begins to transmit another cell. Figure 10 • Read Interface Cell Transfer U1_rx_cl U1_rx_cla U1_rx_en r_buf_en r_data U1_rx_soc U1_rx_data XX H1 H2 H3 H4 H5 P1 P2 00 01 02 03 04 H1H2 H3H4 XX H5H6 P1P2 r_adr Figure 11 • Back-to-Back Read Cell Transfer P47 P48 H1 H2 H3 H4 H5 P1 P2 U1_rx_cl U1_rx_clav U1_rx_en r_buf_en R_avail r_data U1_rx_soc U1_rx_data 00 1B 01 02 03 04 H1H2 H3H4 XX H5H6 P1P2 r_adr |
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