December 2005

v 4 . 0

1

© 2005 Actel Corporation

CoreU1PHY – UTOPIA Level 1 PHY Interface

Product Summary

Intended Use

•

Standard UTOPIA Level 1 PHY Interface to any

ATM Link-Layer Device

Key Features

•

Standard 8-Bit, 25 MHz UTOPIA Level 1 PHY

Interface Complies with the ATM Forum UTOPIA

Specification,

Level

1

Version

2.01

(af-phy-

0017.000)

•

Separate TX and RX Clocks and Interface Pins

•

Supports Cell-Level Handshake for 53- or 54-byte

ATM Cells with Automatic Add/Drop of UDF2 Field

in the ATM Header in 53-byte Mode

•

16-Bit (54-byte) User Interfaces Can be Used

Directly or Bolt-Up to One of Actel's ATM Cell

Buffer Blocks: ATMBUFx

Supported Families

•Fusion

•ProASIC3/E

•

Core Deliverables

•

Netlist Version

–

Compiled

RTL

Simulation

Model

Fully

Environment (IDE)

–

Structural VHDL and Verilog Netlists (with and

without I/O Pads) Compatible with Actel’s

Libero IDE and Industry Standard Synthesis and

Simulation Tools

•

RTL Version

–

VHDL Source Code

–

Core Synthesis and Simulation Scripts

•

Actel-Developed

Testbench

(VHDL)

Fully

Supported by Industry-Standard Simulation Tools

Design Tools Support

•

Simulation: VITAL Compliant VHDL and OVI

Compliant Verilog Simulators

•

General Description

CoreU1PHY is a UTOPIA Level 1 PHY interface core that

connects directly to any ATM link-layer (master) device

and user logic (or optional ATM cell buffer blocks) to

provide an interface between the link-layer device and a

non-standard physical layer device (Figure 1).

Contents

General Description ................................................... 1

Device Requirements ................................................. 2

UTOPIA Interface ....................................................... 2

User Interface ............................................................. 4

Ordering Information ................................................ 6

List of Changes ........................................................... 7

Datasheet Categories ................................................. 7

Figure 1 • Block Diagram

Utopia

Level 1

Link-Layer

Device

CoreU1PHY

CoreATMBUF3

CoreATMBUF3

User

Logic

Other

Device

RX

TX