Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

A54SX08P-1FGG208 Datasheet(PDF) 10 Page - Actel Corporation

Part # A54SX08P-1FGG208
Description  SX Family FPGAs
Download  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A54SX08P-1FGG208 Datasheet(HTML) 10 Page - Actel Corporation

Back Button A54SX08P-1FGG208 Datasheet HTML 6Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 7Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 8Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 9Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 10Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 11Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 12Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 13Page - Actel Corporation A54SX08P-1FGG208 Datasheet HTML 14Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 64 page
background image
SX Family FPGAs
1- 6
v3.2
Boundary Scan Testing (BST)
All SX devices are IEEE 1149.1 compliant. SX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test
pins in conjunction with the program fuse. The
functionality of each pin is described in Table 1-2. In the
dedicated test mode, TCK, TDI, and TDO are dedicated
pins and cannot be used as regular I/Os. In flexible mode,
TMS should be set HIGH through a pull-up resistor of
10 k
Ω. TMS can be pulled LOW to initiate the test
sequence.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown)
is flexible mode.
Dedicated Test Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-7). JTAG pins comply with LVTTL/TTL I/O
specification regardless of whether they are used as a
user I/O or a JTAG I/O. Refer to the Table 1-5 on page 1-8
for detailed specifications.
Development Tool Support
The SX family of FPGAs is fully supported by both the
Actel Libero® Integrated Design Environment (IDE) and
Designer FPGA Development software. Actel Libero IDE
is
a
design
management
environment,
seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Libero IDE
allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment. Libero IDE includes Synplify® for
Actel from Synplicity®, ViewDraw® for Actel from
Mentor Graphics®, ModelSim® HDL Simulator from
Mentor
Graphics,
WaveFormer
Lite™
from
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow diagram (located on the Actel
website) for more information.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven
place-and-route,
and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators, and the
simulation results can be cross-probed with Silicon
Explorer II, Actel integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmartGen core generator, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design. Actel
Designer software is compatible with the most popular
FPGA design entry and verification tools from companies
such as Mentor Graphics, Synplicity, Synopsys®, and
Cadence® Design Systems. The Designer software is
available for both the Windows® and UNIX® operating
systems.
Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to
the PRA/PRB pins for observation. Figure 1-8 on page 1-7
illustrates the interconnection between Silicon Explorer II
and the FPGA to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are
active during probing, critical signals input through
these pins are not available while probing. In addition,
the Security Fuse should not be programmed because
doing so disables the Probe Circuitry.
Table 1-2 •
Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are dedicated
BST pins.
TCK, TDI, TDO are flexible and
may be used as I/Os.
No need for pull-up resistor for
TMS
Use a pull-up resistor of 10 k
Ω
on TMS.
Figure 1-7 • Device Selection Wizard


Similar Part No. - A54SX08P-1FGG208

ManufacturerPart #DatasheetDescription
logo
List of Unclassifed Man...
A54SX08P-1FG208 ETC1-A54SX08P-1FG208 Datasheet
415Kb / 57P
   54SX Family FPGAs
A54SX08P-1FG208I ETC1-A54SX08P-1FG208I Datasheet
415Kb / 57P
   54SX Family FPGAs
A54SX08P-1FG208M ETC1-A54SX08P-1FG208M Datasheet
415Kb / 57P
   54SX Family FPGAs
A54SX08P-1FG208PP ETC1-A54SX08P-1FG208PP Datasheet
415Kb / 57P
   54SX Family FPGAs
More results

Similar Description - A54SX08P-1FGG208

ManufacturerPart #DatasheetDescription
logo
Actel Corporation
A54SX32-TQ144 ACTEL-A54SX32-TQ144 Datasheet
504Kb / 64P
   SX Family FPGAs
A54SX08-TQ176 ACTEL-A54SX08-TQ176 Datasheet
504Kb / 64P
   SX Family FPGAs
A54SX16-P2PQG208 ACTEL-A54SX16-P2PQG208 Datasheet
504Kb / 64P
   SX Family FPGAs
A54SX08A-FTQG144 ACTEL-A54SX08A-FTQG144 Datasheet
823Kb / 108P
   SX-A Family FPGAs
A54SX08A-FTQ144 ACTEL-A54SX08A-FTQ144 Datasheet
828Kb / 108P
   SX-A Family FPGAs
logo
List of Unclassifed Man...
A54SX08A ETC1-A54SX08A Datasheet
720Kb / 108P
   SX-A Family FPGAs
logo
Actel Corporation
A54SX72A-CQ256 ACTEL-A54SX72A-CQ256 Datasheet
823Kb / 108P
   SX-A Family FPGAs
A54SX16A2PQG208 ACTEL-A54SX16A2PQG208 Datasheet
818Kb / 108P
   SX-A Family FPGAs
A54SX16A-TQ100 ACTEL-A54SX16A-TQ100 Datasheet
824Kb / 108P
   SX-A Family FPGAs
A54SX32A-1CQ208M ACTEL-A54SX32A-1CQ208M Datasheet
455Kb / 50P
   HiRel SX-A Family FPGAs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com